Self-Consistent Modeling of Heating and MOSFET Performance in Three-Dimensional Integrated Circuits

We present a new method for finding the temperature profile of vertically stacked threedimensional (3D) digital integrated circuits (ICs), as shown in Fig. 1. Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3D ICs, we solve non-isothermal device equations self-consistently with lumped heat flow equations for the entire 3D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency) and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of lumped thermal network using 3D IC layout. To include software, chip floor plan and duty cycle related performance variations, we employ a statistical Monte Carlo (MC) type algorithm. In this work, we investigate performance of vertically stacked 3D ICs, with each layer modeled after Pentium III [1]. Our calculated results show that layers within the stacked 3D ICs, especially the ones in the middle, may greatly suffer from thermal heating.